Custom IC Design Floorplanning

[dragonfury]

I just need some tips regarding what are the industry trends for complete custom chip layout floorplan?

1. Do custom chip designs have some part of their chip empty to cater for thermal, stress or other kinds of design issues?
2. If yes, then what is the criteria and what amount of chip area is kept vacant (i,e. without any active area)?
3. Is process variations on a single die a main concern for creating such a chip?

Thank you very much.

 

[sarvanbhakya]

watever u r asking is depends on technology..if u r student just follow the tool flow else follow ur industry standard