#### jgk2004

##### Full Member level 5

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I am in the process of designing a new DAC and am having trouble with determining the transistor sizes for a specific matching. I need to size them to have a 7bit linearity with only a 4bit DAC. Now normally at the end I would do a transient simulation and look at the FFT but this takes to long everytime when trying to find the correct sizes. Therefore, I want to just do a mismatch simulation of a small cell and calculate my linearity ruffly to find the correct sizes. Is this possible? My starting was this, I make a current mirror, as shown attached, left side has NO mismatch simulated, while right does have mismatch. The DAC is designed to have unit elements, so I think if I look at one unit element it would be the worst case. Therefore, I then subtract the Ideal current form the mismatched one and then I get a distribution. I know there could be a mean shift but this is ok. Since each unit element is 38uA and I want a 7bit linearity, i take 38uA/2^(7+1) so I am below LSB/2. Is this correct? This then sets my limits which is +-148nA+mean.... I am thinking this is the correct thinking but then when I simulate the DAC in the time domain and take a FFT the linearity is 9 bit, therefore my transistors are WAY OVER sized!!! I want them to be sized correctly. Any help would be great. I just want my little testbench to match my FFT more correctly. I think I am missing something here...

https://obrazki.elektroda.pl/5926546200_1357735209.png

Thanks

JGK