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# [SOLVED]Current Steering DAC Transistor sizes/Overdrive for finding Linearity (Monte Carlo)

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#### jgk2004

##### Full Member level 5
Hello all,

I am in the process of designing a new DAC and am having trouble with determining the transistor sizes for a specific matching. I need to size them to have a 7bit linearity with only a 4bit DAC. Now normally at the end I would do a transient simulation and look at the FFT but this takes to long everytime when trying to find the correct sizes. Therefore, I want to just do a mismatch simulation of a small cell and calculate my linearity ruffly to find the correct sizes. Is this possible? My starting was this, I make a current mirror, as shown attached, left side has NO mismatch simulated, while right does have mismatch. The DAC is designed to have unit elements, so I think if I look at one unit element it would be the worst case. Therefore, I then subtract the Ideal current form the mismatched one and then I get a distribution. I know there could be a mean shift but this is ok. Since each unit element is 38uA and I want a 7bit linearity, i take 38uA/2^(7+1) so I am below LSB/2. Is this correct? This then sets my limits which is +-148nA+mean.... I am thinking this is the correct thinking but then when I simulate the DAC in the time domain and take a FFT the linearity is 9 bit, therefore my transistors are WAY OVER sized!!! I want them to be sized correctly. Any help would be great. I just want my little testbench to match my FFT more correctly. I think I am missing something here...

https://obrazki.elektroda.pl/5926546200_1357735209.png

Thanks
JGK

Just an idea, John. Don't know if this fits:

If your MC limit actually is mean ± (mean/2^8), this comprises many standard deviations. A single std. deviation (1σ) then is much less - means better accuracy.

Just wanted to solve this thread for others if they are having the same problem. So I found a paper that explains it all and my simulation match reasonable well to it after fixing the equation. In using the equation fixed which is proposed in "Modeling of CMOS Digital-to-Analog Converters for Telecommunication by J. Jacob Wikner TCAS2 May 99, and corrected since there is a small mistake. Here is the correct equation

SFDR ~~20log(3Pi/4)+3N -20log(sigmaunit) were N is your DAC resolution, and sigmaunit is the matching error standard deviation.

JGK

Last edited:

SFDR ~~20log(3Pi/4)+3N -20log(sigmaunit) were N is your DAC resolution, and sigmaunit is the matching error standard deviation.

So from a 4bit converter with a (non-)linearity of 9bit (1/512) from your FFT result you'd get
SFDR ≈ 7.44 + 12 - (-54.19) ≈ 73.6 dB
Is that correct?

erikl

See thats the mistake I think, you can't say 9bit is equal to 1/2^9 when looking at SFDR/linearity and I would think its 1/2^(9+1) to be below 1/2LSB. You have to look at the mismatch, if you take the calculated 73.6dB you found, that would be 12bit linear.... Here is my example, each unit cell is 38uA (in my design). If you look back to my MC run in first post, I have a sigma = 310nA, This results in a

SFDR ≈ 7.44 +12 -20log(1-38uA/38.310uA)= 61.27dB, => 61.27 = 6.02N + 1.76 => N = 9.8bit linear which matches my FFT!

Does that make sense?

JGK

Hi Erikl,

So do you agree or disagree? I am confused.... I feel you can do the same basic calculation that you use for ENOB when considering SNR, SNDR, SQNR.... therefore I feel you can do the same thing with SFDR -to- effective number in linearity... How would you look at it... if you have 61.27dB in SFDR how "linear" would you say the ADC is?

JGK

Hi Erikl,

So do you agree or disagree? I am confused.... I feel you can do the same basic calculation that you use for ENOB when considering SNR, SNDR, SQNR.... therefore I feel you can do the same thing with SFDR -to- effective number in linearity... How would you look at it... if you have 61.27dB in SFDR how "linear" would you say the ADC is?

Hi John,
yes, I agree that you can use the same basic calculation method. But it depends also on the bandwidth which is used and considered by the simulation-FFT-MC chain, and - to some extent - on the input signal level, s. e.g. the AD tutorial below:
Rgds, erikl

jgk2004

### jgk2004

Points: 2
Hi Erikl,

Thanks for that pdf. I did not know of the normalization to full scale to ENOB... This has meant I have been reporting my ENOB wrong which is a bummer since if I normalize my ADCs it even look better .

Thanks,
JGK

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