Current Mode Logic implementation for an AND/NAND gate

[ngox]

Hi, I am trying to implement an AND/NAND gate using current mode logic, and seem to have some trouble getting the output to exhibit low jitter. From looking at the transient waveform, there does not appear to be any glaring issues, but upon inspecting the eye diagram, it can easily be seen that the signal is quite poor. I have ensured that all transistors are operating in the saturation region (I've built CML XOR and DFFs with no problem), and have also verified that this is not a speed issue as I have lowered the input rates to drastically low rates, and the problem still persists. If anyone can advise on this matter, it would help a great deal.

Pictures attached are the circuit and waveforms. The inputs go to the wires that are not connected to anything in the schematic. The wave output is that of a NAND logic. Thanks!

 

[crutschow]

First, in current-mode logic none of the transistors should ever saturate; they all operate in the active region to avoid saturation delays.

Second, normally the size of the eye in the eye diagram is determined by the propagation delays, the rise/fall times of the signals, and the time between signal transition, so I don't see how the circuit would fail at low speeds (unless the time between transitions is still short).

 

[ngox]

First, in current-mode logic none of the transistors should ever saturate; they all operate in the active region to avoid saturation delays.

Second, normally the size of the eye in the eye diagram is determined by the propagation delays, the rise/fall times of the signals, and the time between signal transition, so I don't see how the circuit would fail at low speeds (unless the time between transitions is still short).

Hi crutschow, these are not bipolar, and are mosfets, so they should be operating in the saturation region. There is no forward active for mosfets. As for your second point, that is the dilemna I am having. Thanks.

 

[crutschow]

Why are you doing current-mode logic using FETs? :???: It has no significant advantage over standard logic and has the disadvantage of using much more power. CM logic is normally only used with BJTs to eliminate storage delay in the switching transition from ON to OFF.

 

[ngox]

Why are you doing current-mode logic using FETs? :???: It has no significant advantage over standard logic and has the disadvantage of using much more power. CM logic is normally only used with BJTs to eliminate storage delay in the switching transition from ON to OFF.

Even within a CMOS process, CML is still faster than static CMOS logic by far. Also, I do not have a choice of using a bipolar technology; regardless, whether or not I am using a BJT or a MOSFET is not that critical to the problem at hand.

One other thing I should add is that the above circuit, configured as a MUX or an XOR, operates past 10Gbps with no problems, but the simulation waveform above is experiencing issues even at speeds as low as 1.25Gbps.

 

[ngox]

Bump. If anyone has any ideas at all it'd be great. Thanks.

 

[crutschow]

In general, if you have a problem with the eye diagram, it's either because of circuit delays or too high rise/fall times.

 

[ngox]

As I have stated, the same circuit configured as an XOR, DFF, etc. works fine up to 10Gbps, hence my confusion. I have tried bringing the speed down to as low as 500Mbps and still the problem persists, so it really is not a speed issue.

 

[crutschow]

The pattern you posted is not a normal eye pattern, which should show a superimposed rise and fall, and fall and rise of the signal, giving you something like this. You are only showing one edge of the eye.

 

[ngox]

What I posted is the eye for one unit interval. What you posted is simply two UI. Using infinite persistence, the superposition of a rising and falling edge is the same whether I show one edge or two edges. The distortion of the zero-crossings is still present.

 

[crutschow]

The eye is the large center open area between the two sets of rising and falling edges as shown in my reference. It is not the jitter between two simultaneous rising and falling waveforms. When this eye closes it means you can have data errors. The eye is not the small area between simultaneous rising and falling edges.

 

[ngox]

I understand that. I am just saying that what I posted is also an eye diagram. The eye I posted is simply for one unit interval whereas the one you posted is for two. The problem I am having is that the eye I posted exhibits noticeable jitter.

 

[crutschow]

You will always get a certain amount of jitter due to inherent noise in the circuit. Does this jitter cause errors in the operation of the circuit?

 

[ngox]

If you looked at the waveform above, you will notice that that is a substantial amount of jitter. It is not due to inherent noise. The characteristic of random noise results in random jitter which would not result in distinct double edges. And yes, it causes some errors.

 

[crutschow]

If it's not noise then perhaps there is something causing a bias change in the circuit for different states thus affecting the transition time.