I think this circuit tends to balance both output currents by trying to balance both PMOS' SD-voltages (if both resistors have the same value). The currents then are defined mainly by the PMOS' W/L ratios.
Of course this is only possible for (unequal) non-resistive loads, i.e. transistor loads.
The resistors enable the feedback mechanism for the balancing effect, and are necessary to have 2 different current output nodes.
With resistor ratios ≠ 1 , differing SD-voltages (and so output currents) could be defined.