Current Mirror with RES between Gate and Drain

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rightmederek

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Hi all,

I have a question about Current Mirror circuit.

The left circuit of the figure is a conventional current mirror, and the circuit on the right is what i want to ask about. How it works and what the resistors for?

Thanks,
DD


 

I think this circuit tends to balance both output currents by trying to balance both PMOS' SD-voltages (if both resistors have the same value). The currents then are defined mainly by the PMOS' W/L ratios.

Of course this is only possible for (unequal) non-resistive loads, i.e. transistor loads.

The resistors enable the feedback mechanism for the balancing effect, and are necessary to have 2 different current output nodes.

With resistor ratios ≠ 1 , differing SD-voltages (and so output currents) could be defined.
 

The circuit on the right figure is not a current mirror. This kind of circuit is in fact used in fast symetrical OTA to bias loaded current sources. The resistors are used as local CMFB and if their value is lower than 1/gm of fets, then overall OTA bandwith is increased.
 


Hi Dominik,

Are you saying that this circuit is used for CMFB and bandwidth increment?

Can you explain more about how to increase the bandwidth?

Thanks.
 

In classical diode connected fets You have a nondominant pole equal to gm/cgs of these fets. In this LCMFB connection this pole is moved to 1/R·cgs, for R<1/gm.
You can check some papers about classs "super AB" OTA which using it.
 
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    erikl

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In classical diode connected fets You have a nondominant pole equal to gm/cgs of these fets. In this LCMFB connection this pole is moved to 1/R·cgs, for R<1/gm.
You can check some papers about classs "super AB" OTA which using it.

Hi,

You suggest is really helpful.

Since we are talking about OTA, i've seen some circuits that they split the tail current and put res between their sources (As figure). Is it to improve the CMRR or what? If so, then how?

Thanks.

 

This is a simple degeneration of input diff pair, mostly used to enhance linearity, but with cost of input offset.
 

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