Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] current mirror problem

Status
Not open for further replies.

gone

Junior Member level 1
Joined
Sep 27, 2012
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,390
hi all,

i attempt to use a PMOS current mirror to charge up a capacitor, i can generate a 20u current but cannot copy it to the next pmos therefore cannot charge the capacitor....

actually how to use a current mirror to charge up a cap? i am thinking if it's too simple to just connect the pmos current mirror to the cap

thanks
 
Last edited:

i attempt to use a PMOS current mirror to charge up a capacitor, i can generate a 20u current but cannot copy it to the next pmos therefore cannot charge the capacitor....

... i am thinking if it's too simple to just connect the pmos current mirror to the cap

No, it works well (often used). However, you can't load the cap more than the available voltage - then the current flow will stop.
 
I have the same thing when I simulate the operational amplifier, I bias it for example to source 100uA at the load to get a certain S.R, and I get that S.R but when I come see the current I found it less what it supposed to be. isnt the same like problem ? but I am simulating it with D.C where the capacitor is O.C but I dont know Why
 

... the current I found it less what it supposed to be. isnt the same like problem ? but I am simulating it with D.C where the capacitor is O.C ...

This can't be the same pb., as the cap is not existent in DC analysis, as you stated correctly. You can't get the expected current from the mirror ratio, if the Vds voltages of the mirror transistors are rather different, see the Ids vs. Vds characteristic of your transistor, or this posting.
 
the original PMOS does have 20u current flow but the next PMOS is in linear and its current is extremely small

i cant get why

- - - Updated - - -

yes, it does work well, i just forgot to set the initial value in my HSPICE
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top