deveshkm
Member level 4
Hi,
I am designing a differential amplifier for Vdd=1.5 to 1.7 V
Input is PMOS
In order to meet the specifications over PVT and icmr
I biased diff pair in subthreshold. However, due to limited headroom I reduced VDSAT of tail MOS by biasing in subthreshold
I have obtained sufficient bias margin to keep every device in saturation, albeit subthreshold
What are the possible drawbacks of using subthreshold current mirror?
I am designing a differential amplifier for Vdd=1.5 to 1.7 V
Input is PMOS
In order to meet the specifications over PVT and icmr
I biased diff pair in subthreshold. However, due to limited headroom I reduced VDSAT of tail MOS by biasing in subthreshold
I have obtained sufficient bias margin to keep every device in saturation, albeit subthreshold
What are the possible drawbacks of using subthreshold current mirror?