CTS problem in SOC Encounter

[hkrist]

Hi all,

I met a problem when I used SOCE to implement my design.

After the step of CTS, I found the clock tree didn't connect to the pin of clock input pad and the pin of CLK of SRAM macro.

I read the log of encounter and found there were some warnings. I think maybe the warnings are the reason for the above problem.

The followings are the warnings from the log of encounter:

**WARN: (ENCCK-6325): Clock MCK has instance pin PAD_I_MCK/PAD which is far from any legal placement location. The nearest available placement location is at (524.4, 467.6), which is 43.035 microns away.
It may be difficult to drive this pin with an acceptable transition time. Check to make sure that the placement of this instance and the floorplan are realistic.

**WARN: (ENCCK-6335): Clock MCK has leaf pin top_BIST_with_CS_CHIP/sram_2048/CLK, which is considered covered by routing blockages, as it lies in thin channel or congested cells (as per the current blockage modeling in CTS).

Please give me some advice, thanks.

 

[hkrist]

pin connection problem in encounter

Hi all,

In the previous post, I found there is no connection at the pin of clock pad and the CLK of sram macro after CTS.
I think it just happened in clock pins after CTS. However, today I skip the problem and finish doing nanoroute.
Besides clock pins, the other pins in my design are not connected. I don't know why would this happen, please give me some advice.

Thanks.