You should be able to get the Verilog from a schematic design in ISE. The file name should be the same name as the schematic file with ".vf"
You should find this file in your project directory, but you need to make sure your preferred language for the project is Verilog. Otherwise it'll make a .VHF; which is VHDL.
the .VF and .VHF files only exist if synthesis has been run on the schematic at least once. These files are a side-product of the synthesis process so they'll only be present if you've run synthesis at least once (they are removed as part of Cleanup Project Files).