creating an one time delay in vhdl test bench

ananthan95 · Dec 9, 2017

I am trying to write a VHDL test bench. the issue is, I have to write a code in such a way that a delay of 1000ns has to be executed in the beginning and later on the delay period is 620ns. so what should i do?

KlausST · Dec 9, 2017

Hi,

Use a counter with variable "TOP" value:

Example: counter with 100MHz clock.
Counting from 0...99 gives a 1000ns delay
Counting from 0...61 gives a 620ns delay

Klaus

FvM · Dec 9, 2017

Code VHDL - [expand]
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process
  -- action code
  wait for 1000 ns;
  loop
      -- action code
    wait for 620 ns;
  end loop;
end process;

KlausST · Dec 9, 2017

Hi,

yes: test bench

My solution is for chip inside solutions.

Klaus

creating an one time delay in vhdl test bench

ananthan95

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KlausST

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ananthan95

FvM

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ananthan95

KlausST

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Code VHDL - [expand]
1 2 3 4 5 6 7 8	process -- action code wait for 1000 ns; loop -- action code wait for 620 ns; end loop; end process;

creating an one time delay in vhdl test bench

ananthan95

Junior Member level 3

KlausST

Advanced Member level 7

FvM

Super Moderator

KlausST

Advanced Member level 7

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