how to create a clock in verilog
Its slighly difficult at RTL level. You need to estimate the delay of buffers/Inverter pais wrto the target technology . From the set of buffers/Inv pairs u need to select cells, which can contribute 0.4 ns delay . you can take this circuit to delay your input clock to generate the shifted clock.
The problems are : 1) Its diffciut to estimate the delay of the cells with single/multiple runs of synthesis.
2) The design will become entirely technogy dependent.
3) The accuracy of the clock depends on the delay of the cells and edge may not macth some times.
Regards,
Sam