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Create generated clock in RTL( Verilog HDL )

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Full Member level 3
Jul 25, 2007
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generated clock

Hello All,

Do anyone have any idea how to create a generated clock in RTL?.

What i want to achieve here is i want to create CLK2 from CLK1 but
this CLK2 is shifted maybe 0.4n from the CLK1?

CLK1 will directly come from the PLL.
While CLK2 is generated from CLK1.

I will be really appreciate if you can give me some idea how to
implement the CLK2 in RTL. Thanks.

how to create a clock in verilog

Its slighly difficult at RTL level. You need to estimate the delay of buffers/Inverter pais wrto the target technology . From the set of buffers/Inv pairs u need to select cells, which can contribute 0.4 ns delay . you can take this circuit to delay your input clock to generate the shifted clock.

The problems are : 1) Its diffciut to estimate the delay of the cells with single/multiple runs of synthesis.
2) The design will become entirely technogy dependent.
3) The accuracy of the clock depends on the delay of the cells and edge may not macth some times.


verilog create delay

if clock cycle > 0.4 ns, you can simply write assign #0.4 CLK2 = CLk1;
What is difficult is to implement it in physical design.

divide clock by 5 verilog

What is the current practice in the industry to implement generated clock from the clock source?


verilog delay create

clk2 is 0.4ns shift from clk1 is usually done in backend .But i dont think in RTL.In RTL,divide or multiple of clock cna be done. Can any one comment on this.

how to do clock in verilog rtl

Hi All,

I think we can't design delay cell s using the rtl.since the 0.4 ns should always conistant irrespective of the VT there are circuts in the Analog design which will act as a conistant phase shifter.since they use the o/p signal as a feedback signal which will make the phase diffrence as conistant.


pll verilog hdl

Hi all,

Does anyone have any idea how to synthesize a generated clock?.

What i have is CLK2 and CLK1.

Clk1 is global clock.
Clk2 is generated using CMOS logic. Inputs of this CMOS logic comes from gates that use CLK1 as their clock.

What I am trying to build is a self timed circuit. Level-2 waits for Level-1 to complete. CMOS logic in between behaves like a clock generator for level2.

I will be really appreciate if you can give me some idea how to
synthesize this in Cadence RTL complier or in DC with commands that can be feed to RTL complier.


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