[SOLVED] CRC for SENT Protocol

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ctzof

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Hallo,

I want to implement a verilog code for SENT protocol CRC checksum. Is a simple CRC-4 with 1101 as polynom and 0101 as initial seed value. My input is 24- bit and the final crc value is determined by the polynom bit-count as 4 bits. I have tried many configurations but until now none works. I have found the following c-code from infineon which is used as recommendation to one of their datasheet for SENT protocol crc calculations. Can anyone help me into transform this code to verilog code.

 

With whatever knowledge you have, try it our yourself, write a test-bench for your module and see what happens in simulation.
If you then face problems, forum members are here!
 

Actually I found a solution yesterday by using http://outputlogic.com/?page_id=321. I had to modified the code a little bit for the initial seed of d'5 . Below is the code in verilog as a future reference. I have also implement a code based on the transformation of the c code in my first post, it works also but requires more space and clock cycles to be implemented in FPGA.

 

Just one point: crc_out <= crc_en ? lfsr_c : 4'hZ;

If you want to use this crc block as part of a larger design, it is not a good idea to propagate 'Z' to crc_out if crc_en is LOW. Avoid Z's in ckt design wherever possible.
 

Just one point: crc_out <= crc_en ? lfsr_c : 4'hZ;

If you want to use this crc block as part of a larger design, it is not a good idea to propagate 'Z' to crc_out if crc_en is LOW. Avoid Z's in ckt design wherever possible.

Yea, it was just a random choice.
 

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