[SOLVED] CRC for SENT Protocol

[ctzof]

Hallo,

I want to implement a verilog code for SENT protocol CRC checksum. Is a simple CRC-4 with 1101 as polynom and 0101 as initial seed value. My input is 24- bit and the final crc value is determined by the polynom bit-count as 4 bits. I have tried many configurations but until now none works. I have found the following c-code from infineon which is used as recommendation to one of their datasheet for SENT protocol crc calculations. Can anyone help me into transform this code to verilog code.

// Fast way for any µC with low memory and compute capabilities
char Data[8] = {…}; // contains the input data (status nibble , 6 data nibble , CRC)
// required variables and LUT
char CheckSum, i;
char CrcLookup[16] = {0, 13, 7, 10, 14, 3, 9, 4, 1, 12, 6, 11, 15, 2, 8, 5};
CheckSum= 5; // initialize checksum with seed "0101"
for (i=0; i<7; i++) {
CheckSum = CheckSum ^ Data;
CheckSum = CrcLookup[CheckSum];
}
; // finally check if Data [7] is equal to CheckSum

 

[kaiserschmarren87]

This should help you:

http://electronics.stackexchange.com/questions/92529/implementing-parallel-crc-in-verilog

Or else try to generate using online tools:

http://outputlogic.com/?page_id=321
http://leventozturk.com/engineering/crc/

 

[dpaul]

With whatever knowledge you have, try it our yourself, write a test-bench for your module and see what happens in simulation.
If you then face problems, forum members are here!

 

[ctzof]

Actually I found a solution yesterday by using http://outputlogic.com/?page_id=321. I had to modified the code a little bit for the initial seed of d'5 . Below is the code in verilog as a future reference. I have also implement a code based on the transformation of the c code in my first post, it works also but requires more space and clock cycles to be implemented in FPGA.

// CRC module for data[27:0] , crc[3:0]=1+x^2+x^3+x^4;
//-----------------------------------------------------------------------------
module crcj(
input [27:0] data_in,//The computation is performed with data including data (6 nibble) and sync (1 nibble which is alawys 0 for valid transmission) in total 7 nibble=28 bit
input crc_en,
output reg [3:0] crc_out,
input rst,
input clk);

reg [3:0] lfsr_c;


always @(*) begin
//The first values represent the seed which is 4'b0101 (5)
lfsr_c[0] = 1'b1 ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[7] ^ data_in[8] ^ data_in[10] ^ data_in[14] ^ data_in[15] ^ data_in[17] ^ data_in[21] ^ data_in[22] ^ data_in[24];
lfsr_c[1] = 1'b0 ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[8] ^ data_in[9] ^ data_in[11] ^ data_in[15] ^ data_in[16] ^ data_in[18] ^ data_in[22] ^ data_in[23] ^ data_in[25];
lfsr_c[2] = 1'b1 ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[5] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[12] ^ data_in[14] ^ data_in[15] ^ data_in[16] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[26];
lfsr_c[3] = 1'b0 ^ data_in[0] ^ data_in[2] ^ data_in[6] ^ data_in[7] ^ data_in[9] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[20] ^ data_in[21] ^ data_in[23] ^ data_in[27];

end // always

always @(posedge clk, posedge rst) begin
if(rst) begin
crc_out <= {4'h0};
end
else begin
crc_out <= crc_en ? lfsr_c : 4'hZ;
end
end // always
endmodule // crc

 

[dpaul]

Just one point: crc_out <= crc_en ? lfsr_c : 4'hZ;

If you want to use this crc block as part of a larger design, it is not a good idea to propagate 'Z' to crc_out if crc_en is LOW. Avoid Z's in ckt design wherever possible.

 

[ctzof]

Just one point: crc_out <= crc_en ? lfsr_c : 4'hZ;

If you want to use this crc block as part of a larger design, it is not a good idea to propagate 'Z' to crc_out if crc_en is LOW. Avoid Z's in ckt design wherever possible.

Yea, it was just a random choice.