paulki
Full Member level 2
Hi CPU Core guys,
It is very helpful to start a discussion topic on different CPU Core verification methodologies. Area of interests are listed below.
1. Concept of different level of Caches
2. TLB and Caches, Bus Architecture for I&D Caches and TLBs
3. Cache coherency protocol and verification methodologies for the Multi core SoC architecture.
4. RTG based verification (Random Test Generator)
5. C-reference model verification (How the cyclisation can achieve)
6. Branch Prediction and Pipeline Stalls
7. CPU Pipeline verification for Typical 5 stage Pipe CPUs.
8. Why Caches are required? What is the purpose of TLBs (other than Cache).
-Paul
It is very helpful to start a discussion topic on different CPU Core verification methodologies. Area of interests are listed below.
1. Concept of different level of Caches
2. TLB and Caches, Bus Architecture for I&D Caches and TLBs
3. Cache coherency protocol and verification methodologies for the Multi core SoC architecture.
4. RTG based verification (Random Test Generator)
5. C-reference model verification (How the cyclisation can achieve)
6. Branch Prediction and Pipeline Stalls
7. CPU Pipeline verification for Typical 5 stage Pipe CPUs.
8. Why Caches are required? What is the purpose of TLBs (other than Cache).
-Paul