Buriedcode
Full Member level 6
cs4340 project
Hi, I posted a similar question in the DSP forum, probably the wrong place to post it, no-one replied
Well, I have designed a system to convert an audio signal into digita, send this across some sort of wireless link (radio, IR etc..) and then convert it back to analogue. Forward error correction is also implemented.
The system is built, put on boards and all chips have been programmed.
Doesn't work at all.
There are several areas which could be at fault, but I'm sure its either:
The ADC/DAC, or the CPLD's. I'm using Lattices MACH4A5, a 64/32 for the transmitter, and a 32/32 +64/32 at the receiver (a whole CPLD was needed to decode the stream).
As far as conversion goes, using the CS5330A, and its sister chip the CS4330A, both being stereo sigma-delta convertors.
Could the problem be hardware? I've got both boards running from little 5V 100ma regulators, so on the Tx, this must power the CPLD, the ADC and some small analogue stuff. But....on the Rx, 100ma has to power 2 CPLD's as well as the DAC and opamp etc..
Could it be the clocks? I'm using a C-MAC crystal oscillator 12.288Mhz which is connected directly to the CPLD (via internal clock buffer) for both the Tx and the Rx. It's meant to be very accurate with low jitter, but I measured the output at about 9v p-p 8O
I'm confident that these CPLD's can easily do the job of controlling the ADC/DAC, but maybe my design is having trouble in the 'communication' department :roll: The datarate from Tx to Rx is 1.5MB/s. For testing purposes, this is simply a connection from a CPLD pin on the Tx board to a CPLD pin on the Rx board, and then a ground return.
Lastly, the code. I used schematics and ABEL code, which were then connected in a toplevel schematic for each CPLD. It's quite simple. The Tx CPLD reads the ADC data, splits it into 2 bytes, then encodes each byte using hamming coding. These 2 bytes (now 13 bits each) are transmitted each with a start bit, and a stop bit. The Rx simply reads in the bit stream, decodes and merges the two bytes back into a 16-bit word, then writes this to the DAC.
In simulation (lattice) it looks pretty much perfect, with everything well timed and insignificant propegation delay, but alas, the only thing coming out the DAC is very quiet noise (its getting the right control signals, just not the data)
I realise its a lot of information, but I could go on for days, so if anyone has any suggestions of what may be screwing this thing up. Or any ways of circuit debugging that could help me narrow down the problem I would be grateful, I can't sleep untill this is done. (its not important, it just bugs me :evil: ).
Thankyou,
BuriedCode.
Hi, I posted a similar question in the DSP forum, probably the wrong place to post it, no-one replied
Well, I have designed a system to convert an audio signal into digita, send this across some sort of wireless link (radio, IR etc..) and then convert it back to analogue. Forward error correction is also implemented.
The system is built, put on boards and all chips have been programmed.
Doesn't work at all.
There are several areas which could be at fault, but I'm sure its either:
The ADC/DAC, or the CPLD's. I'm using Lattices MACH4A5, a 64/32 for the transmitter, and a 32/32 +64/32 at the receiver (a whole CPLD was needed to decode the stream).
As far as conversion goes, using the CS5330A, and its sister chip the CS4330A, both being stereo sigma-delta convertors.
Could the problem be hardware? I've got both boards running from little 5V 100ma regulators, so on the Tx, this must power the CPLD, the ADC and some small analogue stuff. But....on the Rx, 100ma has to power 2 CPLD's as well as the DAC and opamp etc..
Could it be the clocks? I'm using a C-MAC crystal oscillator 12.288Mhz which is connected directly to the CPLD (via internal clock buffer) for both the Tx and the Rx. It's meant to be very accurate with low jitter, but I measured the output at about 9v p-p 8O
I'm confident that these CPLD's can easily do the job of controlling the ADC/DAC, but maybe my design is having trouble in the 'communication' department :roll: The datarate from Tx to Rx is 1.5MB/s. For testing purposes, this is simply a connection from a CPLD pin on the Tx board to a CPLD pin on the Rx board, and then a ground return.
Lastly, the code. I used schematics and ABEL code, which were then connected in a toplevel schematic for each CPLD. It's quite simple. The Tx CPLD reads the ADC data, splits it into 2 bytes, then encodes each byte using hamming coding. These 2 bytes (now 13 bits each) are transmitted each with a start bit, and a stop bit. The Rx simply reads in the bit stream, decodes and merges the two bytes back into a 16-bit word, then writes this to the DAC.
In simulation (lattice) it looks pretty much perfect, with everything well timed and insignificant propegation delay, but alas, the only thing coming out the DAC is very quiet noise (its getting the right control signals, just not the data)
I realise its a lot of information, but I could go on for days, so if anyone has any suggestions of what may be screwing this thing up. Or any ways of circuit debugging that could help me narrow down the problem I would be grateful, I can't sleep untill this is done. (its not important, it just bugs me :evil: ).
Thankyou,
BuriedCode.