CPLD clock generation question

[Pavithra89]

hi
I need to generate a clock of M rise time and N fall time using coolrunner CPLD where M and N are inputs. I need a basic idea on how to do this. please guide me .
regards

 

[aruipksni]

hi
I need to generate a clock of M rise time and N fall time using coolrunner CPLD where M and N are inputs. I need a basic idea on how to do this. please guide me .
regards

do you mean you want a clock with pulse high width = M, pulse low width = N ?

how to do this :
1. you need to define what is the basic unit of M, N is it time in ns or higher clock cycle time or numbers ?
2. you need to establish the wright clock rate from wich you will create the varying duty cycle clock.
3. then ofcourse you will need at least a counter that will count to max(m,n).
4. then a control process that will activate the counter, and generate the output. (like a state machine).

 

[mrflibble]

Rise/fall time or duty cycle?

Because if risetime, and you want the risetime to be arbitrary then you have to worry about the analog side of it first. CPLD/FPGA cannot just set any random risetime, there's only so many options you have with drive strength etc.