Coupling capacitance in Digital design

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kaushikrvs

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What is the purpose of capacitive coupling in digital design ? I have seen that the difference in arrival times in at various flops might be due to coupling capacitance or PVT variations ..... I need a little more clarity on this topic and will be helpful if some material regarding this is suggested ?
 

I am confused. Coupling capacitance is non-desired effect, it's not like we add it on purpose. Google signal integrity, crosstalk.

Wires couple to each other, and that can harm the cell timing as well as the interconnect timing. PVT variation is another subject, transistors can be faster or slower depending on process variation. Wires can be thicker, wider, leaner, whatever, also due to PVT. That will affect coupling, therefore affects timing.
 

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