Feb 6, 2014 #1 H hithesh123 Full Member level 6 Joined Nov 21, 2009 Messages 324 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,298 Location lax Activity points 3,548 Basic doubt - How exactly does counter reset to zero, once it reaches the max count. I mean how is it implemented/synthesized in the FPGA. The vhdl code would be some thing like if count>15 then count=0; end if;
Basic doubt - How exactly does counter reset to zero, once it reaches the max count. I mean how is it implemented/synthesized in the FPGA. The vhdl code would be some thing like if count>15 then count=0; end if;
Feb 6, 2014 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 it will be a mux on the counter register. The comparator provides the select for the mux.