counter reset in FPGA

[hithesh123]

Basic doubt -
How exactly does counter reset to zero, once it reaches the max count.
I mean how is it implemented/synthesized in the FPGA.

The vhdl code would be some thing like

if count>15 then
count=0;
end if;

 

[TrickyDicky]

it will be a mux on the counter register. The comparator provides the select for the mux.