Counter in verilog that writes and resets at trigger

[qingcong]

Hi all, I will try to explain my problem in a way that makes sense.

I'm trying to write a counter in verilog. There will be a non-periodic pulse that triggers the counter to reset to 0 and start counting again. This is all standard stuff I think. The part that's throwing me off is that when the non-periodic pulse comes in, I also need to write the counter value to an array. I want to write the value that it was on before it reset to 0. Any suggestions or code samples are welcome. Thanks.

 

[TrickyDicky]

Have you even tried to do it yourself? Post your code and the problems you are having so we can help.

 

[ads-ee]

Do you understand how pipelining flip-flops works? Old data in the 1st FF (Q output) is loaded into the next FF in the pipeline on each clock edge irrespective of what in on the D input of the first FF is.

So when the pulse is active write the count value to wherever you want to store it, I.e. another FF or memory. You do this at the same time you enable the clear of the counter...remember this is hardware and things are truely done in parallel.

 

[qingcong]

Do you understand how pipelining flip-flops works? Old data in the 1st FF (Q output) is loaded into the next FF in the pipeline on each clock edge irrespective of what in on the D input of the first FF is.

So when the pulse is active write the count value to wherever you want to store it, I.e. another FF or memory. You do this at the same time you enable the clear of the counter...remember this is hardware and things are truely done in parallel.

This makes sense.