I want to know the way of designing a counter using both the positive and negative edgse of the clock to get output waveforms which are not of 50% duty cycle.
The suggested code isn't synthesizable cause it would require flip-flops that operate on both edges. They don't exist in FPGA or ASICs as far as I know. Also delay statements are usable in simulation only!
Various solutions for frequency dividers operating on both edges have been posted at EDAboard, I assume that you'll be able to find some of them, They are generally using positive and negative clocked flip-flops with combinational logic.
Can u please let me know some websites in Edaboard or any other websites where I can find out solutions of frequency dividers operating in both the edges?