could you please help me by giving the test bench for the below program

[AthiraMajinu]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;

entity corr is
port(clock:in bit;
reset: in bit;
csum : out integer);
end corr;
architecture corr_beh of corr is
signal dcount, intsum : integer := 0;
signal lfsr_reg1: unsigned(9 downto 0):= (others=>'1');
signal lfsr_reg2 : unsigned(9 downto 0):= (others=>'1');

begin
process (clock, reset,lfsr_reg1,lfsr_reg2)
begin

if reset = '0'then
dcount<= 0;
intsum<= 0;

elsif clock'event and clock = '1' then
dcount<= dcount + 1;
intsum<= intsum + to_integer(unsigned(lfsr_reg1 * lfsr_reg2));
if dcount = 1022 then
dcount<= 0;
intsum<= 0;
csum<= intsum;
end if;
end if;
end process;
end corr_beh;

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its a program for cross correlation

 

[axcdd]

Hi,
Please use 'wrap code' for posting code.
I dont see any drivers in a program for lfsr_reg1, lfsr_reg2, so you always gets the same intsum every 1023 cycles.

 

[imbichie]

Hi,

You can refer this link:

https://vhdlguru.blogspot.in/2010/03/how-to-write-testbench.html

in this link there is a counter (test) which have inputs clk and reset and output is a count
which is similar to your design (corr), in your design also there are clock and reset as inputs and csum as output.
Just take the testbench from the link and change the port and dut names and the signal types.

 

[AthiraMajinu]

tq vry1...