Could we write "CLK" based statements in packages?

[xtcx]

Hello guys!, I have a situation for Transmitting a data to PC's serial port. In VHDL So Whenever I need to transmit I will use a flag at the begining and ending of the UART statements to control the transmission so that it does transmit only when I really need to. Since I am more frequently in need of sending data to the Serial port, so I think of describing the transmission part in Packages(using Procedure). All I wanna know is that can I pass the CLK as the argument along with my data to that package?... Is it possible in VHDL to write CLK based routines inside Packages\procedures?...Please suggest me some,Thanks in Advance..!

 

[FvM]

Re: Could we write "CLK" based statements in packa

The Synopsys VHDL Reference Manual has a slogan-like paragraph title in this regard: Subprogram Always a Combinational Circuit. By basic VHDL rules, you can't use a process in a subprogram body. The intended functionality has to be coded as a component.

 

[nitin_ndg]

Re: Could we write "CLK" based statements in packa

Yes you can use .
i have used clk in PKG. Even i have made my own function "rising_edge" and falling_edge". it works....

 

[FvM]

Re: Could we write "CLK" based statements in packa

The intention, as I understood, was to use a sequential process within a subprogram. I don't see, that this is a supported VHDL construct, but I'm always motivated to learn new things.

The IEEE standard package function rising_edge() is of course using a clock, but it's not involving clock sensitive sequential code in subprogram body, it's just evaluating an input signal and in so far still combinational logic.

 

[xtcx]

Re: Could we write "CLK" based statements in packa

rising_edge() is of course using a clock, but it's not involving clock sensitive sequential code in subprogram body, it's just evaluating an input signal and in so far still combinational logic

Hi FVM, I still can't get your idea, you mean that any statements follwed by the rising_edge() could also be combinatorial?. How?. As you mention "rising_edge()" all the events written under that will be scheduled for the next clock, then how can it be combinatorial?..Be it a subprogram or not!...Any clock based statements are naturaly sequential. So what's the final point, wheter Clk based statements (Process) can be written in subprogram? or just the combinatorial?..If the answer is latter, then I believe the purpose of writting macro is of very little or of no use...
Thanks...

 

[FvM]

Re: Could we write "CLK" based statements in packa

I didn't say, that code followed by rising_edge() is combinational. I said, that the rising_edge() function itself is combinational, although it uses a clock.

But I'm still sure, that it's not possible in VHDL to write CLK based routines inside Packages\procedures, if this means a sequential process inside the procedure.