Could I2C work without a higher speed clock?

[xiaojigao]

Recently I'm coding an I2C slave interface using HDL(verilog). In I2C specification, there is only two line: SCL and SDA. I've searched a lot of example design, they all use a higher speed clock to sample SCL and SDA, and then judge Start/Stop condition. The internal logic are also work at this higher speed clock.
My question is: can I code an I2C interface logic which only use SCL and SDA? If there is no higher speed clock, could I2C controller work well?
Many thanks if any sample code is available!
Thanks a lot!

 

[FvM]

Designing an I2C interface without internal (fast) clock targets to a fully asynchronous design. It's surely possible most simple I2C interface chips, e.g. PCF8574 are designed this way. Besides asnychronous logic they also rely on glitch filters to meet the I2C specification. I doubt that you find sample designs, but why not design it from the scratch?

 

[xiaojigao]

Thank you very much! But I have no concept of "asyncronious circuit design". Maybe I should read some books about this field~~~