you can write once and then cycle the read test. This will show if your theory is correct. Likewise, you can check to make sure you never write that to device.
It it the same bit that fails every time. However a 16b device with a burst should be holding that line low. This is also odd because 128MB @ 32bit means that bit shouldn't even be set within the FPGA logic, so a 1 should never be written on that line.
The only other thing I can think of now is if you have the DCI settings on the device correct. If you don't have the calibration resistors, or if the power to the back is not correct during/after FPGA power on, the output impedance might cause some issues. I wouldn't expect it to cause this exact issue, but I could accept it.