Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] correct my counter please

Status
Not open for further replies.

lolitta73

Newbie level 1
Joined
Apr 20, 2011
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,296
I want that someone correct this code of a simple counter that increment each rising_edge of a signal in input.
-- ================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ================================================================================
entity counter_1 is
port
(
clk: in std_logic;
aclr: in std_logic;
input_s: in std_logic;
output_2: out std_logic
);
end counter_1;
-- ================================================================================
architecture structure of counter_1 is
signal interval_output_2 :std_logic;
begin
-- ================================================================================
-- generate interval_output2
process(clk,aclr,input_s)
variable s:integer:=0;
begin
if aclr='1' then
interval_output_2<='0';
else
if rising_edge(clk) then
if rising_edge(input_s) then
s :=s+1;
end if;
if (s= 0 mod 2) then
interval_output_2<='1';
end if;
end if;
end if;
end process;
-- output output
process(interval_output_2)
begin
output_2 <= interval_output_2;
end process;
-- ================================================================================
end structure;
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
47,489
Helped
14,048
Reputation
28,351
Reaction score
12,706
Trophy points
1,393
Location
Bochum, Germany
Activity points
276,162
Code:
if rising_edge(clk) then
if rising_edge(input_s) then
That's simply nonsense code, you can't chain edge sensitive conditions. If input_s isn't toggling too fast, you may want to use a synchronous edge detection instead.

Code:
if rising_edge(clk) then
input_s1 <= input_s;
input_s2 <= input_s1;
if  input_s1 = '1' and input_s2 = '0' then
s :=s+1;
end if;
if (s= 0 mod 2) then 
interval_output_2<='1';
end if;
end if; 
end if;
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top