#### lolitta73

##### Newbie level 1

-- ================================================================================

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ================================================================================

entity counter_1 is

port

(

clk: in std_logic;

aclr: in std_logic;

input_s: in std_logic;

output_2: out std_logic

);

end counter_1;

-- ================================================================================

architecture structure of counter_1 is

signal interval_output_2 :std_logic;

begin

-- ================================================================================

-- generate interval_output2

process(clk,aclr,input_s)

variable s:integer:=0;

begin

if aclr='1' then

interval_output_2<='0';

else

if rising_edge(clk) then

if rising_edge(input_s) then

s :=s+1;

end if;

if (s= 0 mod 2) then

interval_output_2<='1';

end if;

end if;

end if;

end process;

-- output output

process(interval_output_2)

begin

output_2 <= interval_output_2;

end process;

-- ================================================================================

end structure;