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Correct IO Standard for 125MHz signal..

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Advanced Member level 4
Dec 5, 2004
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I am designing high speed transceiver on PCB, which has ADC signals which are interfaced to Spartan 3A FPGA at Bank 3 by LVPECL standard. This interface works at 250MHz.
Signals from the Bank 1 of this Spartan 3A FPGA are interfaced to I/O of Spartan 3 FPGA. These signals works at 125 MHz. Presently these signals are at LVCMOS_3V3 standard. I will like to know which is correct standard I should use for connection of 125MHz signals from one FPGA to other FPGA ?

spartan 3 iostandard


LVCOMS_3V3 at 125MHz is inviting for trouble.

1. EMI issues, because of high signal voltage.
2. signal integrity, because of the lack of proper termination.

Spartan-3E does have true differential termination in its IOBs which can be used in a 2.5V bank with LVDS. You can use LVDS with the attribute DIFF_TERM attribute to TRUE.

Or you can try LVDCI or LVCOMS_2V5.

how to specify iostandard in ucf file spartan 3

Hi Mta97e,
Thanks a lot for your reply.
I will like to know whether non-differential standard LVTTL can also work ?
Also, is there data on maximum possible signal frequency supported by different IO standards.


spartan 3a io speed mhz lvttl

non diferential signal woulud work for 125MHz. But I am not so sure it would work with LVTTL.

You can try this setup. Define transmit prots as LVDCI and receieve prots as LVCOMS2V5.

Thers is no such specification on maximum data rates supported by various I/O stardards. The performance of any PCB data or clock path is dictated by a number of variables that can only be accounted for through accurate IBIS simulation and power network analysis. Briefly, these variables are

- Output buffer characteristics.
- PCB trace parameters such as characteristic impedance, length, and termination.
- Timing requirements of the design. For example, double data rate (DDR) requires a perfect 50/50 duty cycle, and duty-cycle distortion is common at high speeds.
- Jitter, including clock-source jitter, jitter added by Digital Clock Managers (DCMs) and Delay-Locked Loops (DLLs), jitter caused by SSOs, jitter caused by crosstalk-induced delay variations on the PCB traces, and jitter added by external components such as PLLs.
- The amount of noise present in the system, which is related to the following:

Power consumption (always design-dependent in programmable devices)
Power supply bypassing
Outside EMI sources
Crosstalk on the PCB traces
Simultaneous switching outputs (SSOs)

Xilinx provides IBIS models for simulating data and clock paths on the PCB. However, there are some limitations on the information that IBIS models can provide

differential signal buffer for spartan 3a

Thanks again..
I am not been able to locate the IO standard LVDCI in Spartan 3 and 3A.
Please help me in locating this..

diff_term spartan 3a

Spartan 3 supports LVDCI standard but I am not sure about spartan3A .

if u r using ISE,

user Constraints -> Assign Package Pins and I/O pins, package View will allow you to assign the I/O standard.

Or you can define in your UCF file.
NET "C1_DC_in<0>" LOC = "Pxx" | IOSTANDARD = LVDCI_25 ;
NET "C1_DC_in<1>" LOC = "Pxx" | IOSTANDARD = LVDCI_25 ;

I am not sure what limitations applies in defining LVDCI, such as certain banks only allow you to define LVDCI .... etc. You will have to check against the datasheet.


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