corner case in verilog code.........

[sareene]

verilog corner case

Hi Everyone, The following is a small verilog code which below models a flip-flop with asynchronous set/reset logic (active low). The model synthesizes correctly, but there is a corner case where simulation results are incorrect. What is the corner case?


always_ff @( posedge clk
or negedge rst_n // active-low reset
or negedge set_n // active-low set
)
if (!rst_n) // reset has priority over set
q_out <= '0; // reset all bits to zero
else if (!set_n)
q_out <= '1; // set all bits to one
else
q_out <= data_in; // d input assignment

 

[dcreddy1980]

Look at when you assert the set and reset signal with respect to the clock, Since these two are asynchronous signals, they seem to work fine with the RTL code but you may face problems in the gate level simulation after the block is synthesized.

 

[ljxpjpjljx]

yes, you should consider the synthesis process!

 

[jaydip]

What hardware did you get out of this code? May be you had planned to generate flop. But I am afraid that this code will give you flop ....

 

[ankurgupta74]

set-reset priority depends on the lib. u r using.