Corner analysis & Process variation?

variation of pvt for corners

process variation: relates to change of functioning of MOS (PMOS or NMOS), Capacitor,Resistor.
this means in actual chip where you have 1000s of transistors , you can actually expect that some MOS will be working at different speed(i mean Vt,mobility etc. will be different )

The corner simulation you do actually take into account of this process variation and other variations also like current (if you have current source) voltage (VDD) variations...(generally 10-15%)
so its right that if at all corners your simulation is working then ON -Chipit will (assuming no other eorros done )

corner analysis supply variation

evilguy said:

sparso said:

evilguy said:

So, if we want to assure our design is robust, how many corner we have to consider? is this corner analysis represent process variation in ic fabrication?

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If you are doing purely digital design you can do the following as minimum number of corners:
TTT
SSS (-20% or process dependent)
FFF (+20% or process dependent)
TFS
TSF

For mixed signal stuff you need to add the I/O nMOS and pMOS to the list so it would look like:
TTTTT
SSSSS
FFFFF
TFSFS
TSFSF
TTTSS
TTTFF

Hope that helps.

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what the meaning of those? can you explain further in detail? thank you

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For Example:

TSFSF:

First T: Typical Poly CD (Critical Dimension)
S: Slow core noms
F: Fast core pmos
S: Slow I/O nmos
F: Fast I/O pmos

and so on. This might be slightly different for the different processes. You may have to work with your FAB or Foundry to get the exact breakdown. But the basic idea is to get a good mix of devices.

process variation ic

If your have model files for slow (S), nominal (N) and fast (F), and you want to run your sims over temperature variations (say, from -40 to 125 C), I think a minimal set of 27 runs would be need:
- 3 for temperature - -40, 27 and 125
- 3 for processes - S, N and F
- 3 for design variables (bias currents, power supplies, etc).

So, 3*3*3 = 27.

That would cover a good set of conditions.

Of course, it doesn't cover mismatch. In this case, a MonteCarlo sim would be need.

process variation in spice analysis

It's very useful information. I have already applied this when I was designing using CMOS process with Cadence tool.
Now I have a project with pHEMT process (WinFoundry) designed with ADS. Could anyone help me to have corner analysis in this case?

what is most true about process variation

Yes, corner analysis confirm your design work under all process condition.