CORE power ring width determination

[vikramc98406]

Can anyone brief me about
How to calculate CORE power ring width.

I am actually concerned about, how to determine, vertical strap width and repitition(pitch).

 

[hiral.kotak]

Hi,

Pls visit the site: https://asic-soc.blogspot.com/2007/10/power-planning.html
You will find useful information for poweplanning.

It may help you.

Thanks..

HAK..

 

[vikramc98406]

hi, hiral.kotak

Thanks for the pointer.

can you give me more understanding on how refresh vertical strap width and spacing is determined.

i guess it does not only depends on horizontal row straps but on electro magnetic field current passing through the VDD/VSS pairs.

hope i am clear

 

[t.karteek]

Hi,
Can any one provide me information, on what factors do the power rings' power straps', and power rails' widths depends on? Is it plainly on IR Drop..? What would be the appropriate widths of these..?

 

[raki31]

HI everyone, Here comes all answers for ur doubts,

Power is an important factor for any Design....

there is a certain sequence of steps to calculate WIDTH OF STRIPES AND THEIR SPACING in order to have equal power distribution and to reduce IR-DROP...

1) calculating rough power estimation :-

RoughPwr = (pwr of NAND2) * [(area of block) / (area of NAND2)] * area Utilization

2) Estimating Power stripe Width :-

WIDTH of Vertical Stripe shd be multiples of Vertical routing pitch but less than max value of spacing rule. this value is appox 4 times width of min NAND2 gate value.

WIDTH of horizontal stripe shd be multiples of standard cell height ( preferably one or two times)



if u have any query on this statement plz feel free to comment.......Thanku