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Coolrunner-ii 'high-speed' design questions

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Newbie level 6
Jul 5, 2011
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Hello everyone,
I apologize for the vague title, but I had a few questions and I figured I would roll them into one thread.

I am working on a 'high-speed' cpld design. I put 'high-speed' in quotes since I seem to be in this nebulous region between regular speed and true high-speed.

The design will be interfacing, configuring, controlling and serializing data from a multichannel ADC. There will be a bunch of channels, sampled at a few different rates, there is a large disparity between the required sample rates of the fastest and slowest signals. I am estimating that there will be 10-20 Mbits worth of data being sent serially over a fiber, including an embedded clock (probably Manchester encoding or something similar). There will be a cpld on the receiving end as well. It will perform the separation of the clock and the data. So with 10x over sampling the clock would need to be between 80MHz and 160MHz on the receiving end. The resulting data and clock will go into another device for processing.

So my questions:
1) It seems that clocks up around the 150MHz range are mostly available in differential signaling forms. That would make sense, but what do people usually do in the case of a coolrunner-ii, which doesnt support differential signaling. I have found the occasional device like this one: Vectron Products - Standard Crystal Oscillators (XO) - VCC1 , which supports TTLCMOS. I just dont want to get myself into trouble by using something that doesnt appear to be typical This appears to also be the case with most optical transceivers.

2) Do I forget about a 160MHz clock and just say that if I need a clock that fast then I should just use an 80MHz clock and a frequency doubler? (A dual edge flip-flop available on the coolrunner-ii)

3) Can anyone suggest a better method for what I am doing?

4) Is getting an adjustable clock dangerous for any reason? It would be nice to have a clock which would could be adjusted via SPI or I2C, just in case the design changes, or needs to be re-implemented for something else.


I did something similar a long time ago with a Coolrunner - sending mixed audio, sometimes video and also other digitized data down a fibre. I picked a fixed data rate that would cope and stuck with that all the time. Other details are a bit hazy - it was maybe 10-15 years ago.


Well thats good to know. It certainly seems like its a fairly standard application, I am just hoping to avoid some pitfalls.

I hope the Xilinx software is better than is was 10 years ago. I originally used the Coolrunners when Philips did it and it was fine. Then Xilinx bought it and it was a disaster. I just dug out my documentation for the project and it seems I had a lot of problems with design tools and programming. If you need details I could share them privately but hopefully they have been sorted out now. It seems that I had to abandon doing it in Verilog and due to poor ABEL support in the new Xilinx tools at the time I designed and simulated it using Altera's tools and imported the TDO file in to the Xilinx software for fitting.

My design ran fairly slowly because I was trying to transmit data over 5km of fibre using a battery powered device so I ran the fibre optic transmitter fairly low to save power.


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