ini: process ( armclkout, inistatus )
begin
if ( rising_edge( armclkout ) ) then
soiclkcon <= soiclkcon + 1;
if ( soiclkcon = spiclk_gen ) then
soiclkcon <= x"00";
spiclk <= not spiclk;
elsif ( soiclkcon = x"1F" and spiclk = '0' ) then
case inistatus is
when x"00" =>
..
when x"01" =>
..
when others => null;
end case;
end if;
end if;
end process;
In this code I am using a clock divider to generate a new clock from 50MHZ to 400KHZ.
“elsif ( soiclkcon = x"1F" and spiclk = '0' ) then” this line is used to capture data in 400KHZ domain.
The FSM is use for data processing in 400KHZ domain.
1. inistatus in the sensitive list doesn't have any effect, it's simply superfluous. I guess, it could be from a temporarily removed reset condition.
2. multiple assignments to a signal within a sequential block create well-defined behaviour, thus it's not an error and, as in the example, may be used shorten the code. But I agree, that for clarity and reuseability, I should be better avoided.
I don't think it is good because your syntizise tool will have a chlenge to implimented and might not recognize state machine
Firstival I am using you running SPI device (by your signal name) then why do you have to be so accurate with output frequncy. Use regular counter to divide your input frequncy and use that signal to drive your SPI
then in your state machine
a <= '1' when soiclkcon = x"1F" and spiclk = '0' else '0';
inistatus1 < inistatus & a;
.................
case inistatus1
when "000000001" =>
......
Please also pay attention if you have big state machine becaise it seems your FSM can take up to 256 states