conversion error please help?????

conversion gives error code is
stdtst.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package intest is
subtype bits is std_logic_vector(7 downto 0);
function bconv(bits: std_logic_vector) return integer;
end package intest;

package body intest is
function bconv(bits: in std_logic_vector) return integer is
variable result : integer;
begin
-- result:= std_logic_vector(unsigned(bits,8));
result := to_integer(unsigned(bits));
return result;
end function bconv;
end package body intest;
it compile very well but problem is in second file
stdtstm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.intest.all;

entity test is
port (inbits : in std_logic_vector;
res: out std_logic_vector);
end entity test;
architecture bev of test is
begin
pr: process is
variable temp: integer :=0;
begin
temp := bconv(inbits);
res<= std_logic_vector(unsigned(temp,integervalue));-- integervalue is 8;
end architecture bev;

std_logic_vector(unsigned(temp,integervalue)); gives error;
i use integervalue here because my browser convert it to smily face like 8)

What is integervalue? I don't see a declaration.

"to_unsigned()" is the function you want. "unsigned()" only takes 1 argument.