Converge problem in latch circuits

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020170

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When I simulation only one latch circuit, I have no converge problem and I can get reasonable result.

But I simulated many latch circuits by using hspice, I often don't get any result because of converge problem.

Sometimes, simulation is working properly, amazingly. but resulting waveform is weird.

Is there any one who have same problem like me?

How can I solve this problem?

thanks.
 

sometimes we can try to use a pwl input wave to solve the converge problem , maybe. for example,
v0 vdd 0 pwl 0 0 1u 3.0
 

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    020170

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To solve the DC converge problem in latch circuits , use command "noseset" to set one of the cross-couple nodes to power or ground.
 

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    020170

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You need to give an initial condition for the output node.

Ex.
.ic V(out)=0
 

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    020170

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using PWL source can solve, because ur latch's inital is uncertainty, hspice can't find the converge solution

stoned
best regards
 

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    020170

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most probablt PWL signal will spve ur prob. othrwise try to play with abstol reltol values
 

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