@FvM and @nisshith
Yes. I realized that by writing and testing some sample code by writing in the above way.
Verilog module
module conv_int (b,a);
input [2:0] a;
output reg b;
integer i = 2;
always @(*)
begin
if( i == a[1:0])
b <= 0;
else
b <= 1;
end
endmodule
VHDL module (equivalent)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity conv_int is
port(a : in std_logic_vector(2 DOWNTO 0);
b: out std_logic);
end conv_int;
architecture beh of conv_int is
signal i : integer := 2;
begin
process (a,i)
begin
if ( i = conv_integer(a(1 DOWNTO 0))) THEN
b <= '0';
else
b <= '1';
END IF;
end process;
end beh;
The RTL views are in the images 1 and 2 respectively.
Per Verilog design RTL view, comparison is 32-bit. 32-bit integer and 30-bit vector(although it is declared as 3 bit)
Per VHDL deisignRTL view, comparison is 2-bit, which is optimized.
How can this be more optimized in Verilog?