[SOLVED] CONV_ question in VHDL

[dfxu123]

HI,

i have a trouble in understanding conv_ word.

let's say, X<=conv_std_logic(Y,8), It's could mean that cpnv a 8 bit vector X to a integer Y has range 0-255.

But, what if we get a A <= CONV_STD_LOGIC_VECTOR(8,10); or B <= CONV_STD_LOGIC_VECTOR(320,10); IS this mean convert a 10 bit vector to 8 and 320 integer? Or Is it mean someting else?

Thank you

 

[TrickyDicky]

the conv_std_loigic_vector function is provided by non-standard VHDL libraries. They allow you to convert the integer Y into a N bit vector, X. So whatever Y is, the output is 8 bits. If Y is 257, X will be "00000001". But conv_std_logic_vector is provided in 2 places, and could convert a signed or unsigned integer.

I wouldnt recommend using non_standard libraries. The recommneded library is numeric_std (delete any references to std_logic_signed or std_logic_unsigned and std_logic_arith). then you can use much more meaningfull conversion functions:

X <= std_logic_vector( to_unsigned( Y, 8 ) );

 

[dfxu123]

Well,I got your point.Thanks a lot.