Controller area network (can)

[rajusripathi83]

HI,

In CAN rtl we have blocks like
can_fifo.v
can_bsp.v
can_registers.v
.
.
.

what are they?

can any body explain me the architecture of CAN.

and block level diagram for CAN to write a verilog code?

how to start a verilog code for CAN?

 

[FvM]

Refer to the general CAN documentation and the VHDL reference design.
**broken link removed**