[SOLVED] Control voltage range of VCO

[Engineer4ever]

Hi,

I am designing an Injection-Locked Oscillator using a circuit that resembles that one, and I need to know how to determine the limits of Vctrl. I applied the condition: Vds<<2(Vgs-Vth) on the PMOS transistors (deep triode region) to get the upper value of Vctrl, but I don't know how to get its lower acceptable value. Any help?



Thanks,

 

[dick_freebird]

If you're set up for SPICE analysis then I'd just step
through the practical range (0 - VDD) and observe
waveshape and frequency; you can pick off the freq
value by an expression and plot vs the VCONT value
(either in a decent waveform viewer, or exported to
Excel).

Depending on what you want the control range might
vary; for example if you wanted a pure sine output,
you'd need to stay out of clipping but for digital, may
have more usable range (until duty cycle distortion,
maybe).

 

[Engineer4ever]

If you're set up for SPICE analysis then I'd just step
through the practical range (0 - VDD) and observe
waveshape and frequency; you can pick off the freq
value by an expression and plot vs the VCONT value
(either in a decent waveform viewer, or exported to
Excel).

Depending on what you want the control range might
vary; for example if you wanted a pure sine output,
you'd need to stay out of clipping but for digital, may
have more usable range (until duty cycle distortion,
maybe).

Thanks for your reply.

So, is there no way to calculate an approximate value by hand analysis before simulation? I mean, how can I size the transistors properly if I don't have approximate values of Vctrl?

 

[dick_freebird]

Sizing follows the desired function / characteristics.
You could size the load FETs across more than a 10:1
range and still have gross functionality just by varying
VCTRL to compensate. But knowing what you're tuning
toward, that's the lead question. If this is a stage of
a ring oscillator then maybe VCTRL-set bias current
determines the fOsc (with the shunt C values and stray
capacitance). That's another job for SPICE (I would not
presume to do a good / complete job of expressing the
operation in a closed form equation, to solve).

 

[Engineer4ever]

You could size the load FETs across more than a 10:1
range

I am sorry but I don't know if I understand this part correctly. Do you mean sizing the PMOS transistors up to 10x their standard size (depending on the technology I am working on)?

 

[dick_freebird]

I'm saying they are dumb current sources and can
be throttled to the same drain current, by VCTRL,
whatever their size may be (within reason).