Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Control Unit and ALU Control Op

Status
Not open for further replies.

er693310

Newbie level 1
Joined
Dec 5, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,304
Hello everyone. I'm designing a control unit for a simple 32 bit mips CPU. For some reason, when I give the Control unit a subtract instruction, it will treat it as an add (ALUControl for sub is 110 and ALUControl from add is 010).

I've attached my code here, could someone tell me what's wrong? I've monitored all the bits coming into ALUControl[2] (i.e., funct[1], ALUOp[1], and ALUOp[0]) and they've been 1, 1, and 0 respectively. Thus, I should get 110 from my ALUControl! Please help me!

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Control Unit Module
//////////////////////////////////////////////////////////////////////////////////
module Control(opcode, funct, ALUSrc, ALUOp, RegDst, MemWrite, MemRead, Beq, Bne, Jump, MemToReg, RegWrite, ALUControl, Control);

input [5:0] opcode;
input [5:0] funct;

output ALUSrc, RegDst, MemWrite, MemRead, Beq, Bne, Jump, MemToReg, RegWrite;
output [1:0] ALUOp;
output [2:0] ALUControl;
output [8:0] Control;


reg ALUSrc, RegDst, MemWrite, MemRead, Beq, Bne, Jump, MemToReg, RegWrite, Branch;
reg [1:0] ALUOp;
reg [2:0] ALUControl;
reg RFormat, lw, sw, beq, bne, jmp;
reg [8:0] Control;
reg [3:0] EX;
reg [2:0] M;
reg [1:0] WB;

always@(opcode)
begin
assign RFormat = (~opcode[5] & ~opcode[4] & ~opcode[3] & ~opcode[2] & ~opcode[1] & ~opcode[0]);
assign lw = (opcode[5] & ~opcode[4] & ~opcode[3] & ~opcode[2] & opcode[1] & opcode[0]);
assign sw = (opcode[5] & ~opcode[4] & opcode[3] & ~opcode[2] & opcode[1] & opcode[0]);
assign beq = (~opcode[5] & ~opcode[4] & ~opcode[3] & opcode[2] & ~opcode[1] & ~opcode[0]);
assign bne = (~opcode[5] & ~opcode[4] & ~opcode[3] & opcode[2] & ~opcode[1] & opcode[0]);
assign jmp = (~opcode[5] & ~opcode[4] & ~opcode[3] & ~opcode[2] & opcode[1] & ~opcode[0]);

assign RegDst = RFormat;
assign ALUSrc = (lw | sw);
assign MemToReg = lw;
assign RegWrite = (RFormat | lw);
assign MemRead = lw;
assign MemWrite = sw;
assign Beq = beq;
assign Bne = bne;
assign Jump = jmp;
assign Branch = beq | bne;

ALUOp[1] = (RFormat | jmp);
ALUOp[0] = (bne | beq | jmp);

// Execution control
EX[3] = RegDst;
EX[2] = ALUSrc;
EX[1] = RFormat;
EX[0] = Beq;

// Memory control
M[2] = Branch;
M[1] = MemRead;
M[0] = MemWrite;

// Write-back control
WB[1] = MemToReg;
WB[0] = RegWrite;

// Final control
Control[8:7] = WB;
Control[6:4] = M;
Control[3:0] = EX;

ALUControl[0] = (funct[0] | funct[3]) & ALUOp[1];
ALUControl[1] = (~funct[2] | ~ALUOp[1]);

ALUControl[2] = funct[1] & ALUOp[1] | ALUOp[0];

end



endmodule
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top