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Control the power off sequence in sw regulator

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flote21

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Hi guys!

I need to delay the power off sequence of two sw regulator. Normally it is relatively easy to control the power up sequence through the enable pin, however the power off, how can assure that on one of the sw regulator is "alive" more time than the other? Se below the required power down sequence:

1628508292214.png


I have been thinkin to delay the ouput +0V9 volt with a PMOS transitor and a RC connected to the gate but I want to know if there are other options...

thanks in advance.

Greetings.
 

Hi,

the LTC3612 has an enable pin (RUN; active high). By pulling this pin low the LTC3612 will be disabled. A possebility to achive a delayed turn off is a RC circuit including a diode. Use a high valued resistor and a diode in parallel, but a capacitor to the cathode, which is connected to the enable (RUN) pin. The diode ensures a fast turn on (HIGH signal at the anode), when pulling the control signal at the anode to GND, the capacitor will be slowly dischaged via the resistor (the diode blocks the current flow).

BR
 

Hi,

disabling an SMPS IC does not necessarily mean the the voltage drops.

Wheter and how fast it drops depends on the capacitors an the load current.

So even if you disable them in the right manner .. the voltage is something different.

****
Timing for the ENABLE signals:
Could be done with R, C, D:
1.8V: delayed turn ON, fast turn OFF
0.9V: fast turn ON, delayed turn OFF

Klaus
 

    flote21

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There are sequencer chips but not real popular I think. The down-ramp is not controlled on many dc_dc parts unlike soft start / pgood on the rising input supply edge.
 

Hi,

Embarrassing, annoying is that I can't find the very useful pdf about assorted gate drive circuits with adjustable on-delays and off-delays that I copied several useful on-delay and off-delay circuits from, despite searching online and looking in my folders for the past 30 minutes..., embarrassing is uploading this jpg of gate drive examples from said application note which I simulated before choosing the most convenient one to use in a circuit - I mainly want to draw your attention to 'e) different switch-on and switch-off requirements', it was also okay (not a PITA) to use and adjust in the real world as far as I remember.

GATE DRIVE EXAMPLES V1.JPG
 

Hi!
KlauST is right. Controlling the enable pin of the regulator is not enough to assure a power down sequence.
As far as I could check there some regulators with the feature "Output Capacitor Discharge Function" like the part from TI: TPS62067.
Probably the easiest solution would be to exchange my regulators by this one.
What do you think? Any better idea?
Greetings
 

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