mvj
Advanced Member level 4
Hi All,
referring to the cirucit shown in the image below, either of the swtiches are closed such that the load capacitor is either conneted to Vref or 0V. May I know if the control signals A and A_BAR should not be overlapping at any cost i.e. there should not be a period of time over which both of them are on?
I think that an overlap of the control signals would mean shortingt the supply to ground and should be avoided, is it not?
THanks,
M
referring to the cirucit shown in the image below, either of the swtiches are closed such that the load capacitor is either conneted to Vref or 0V. May I know if the control signals A and A_BAR should not be overlapping at any cost i.e. there should not be a period of time over which both of them are on?
I think that an overlap of the control signals would mean shortingt the supply to ground and should be avoided, is it not?
THanks,
M