Dec 25, 2009 #1 V vlsi_006 Newbie level 4 Joined Dec 10, 2007 Messages 7 Helped 0 Reputation 0 Reaction score 1 Trophy points 1,281 Activity points 1,341 Most of the control signals such as reset, CE, etc. in most of the IC's are active low why?
Dec 28, 2009 #2 L ljxpjpjljx Advanced Member level 3 Joined May 5, 2008 Messages 968 Helped 80 Reputation 162 Reaction score 56 Trophy points 1,308 Location Shang Hai Activity points 4,679 the common usage for us! you can also use the protocol you define!
Dec 29, 2009 #3 S Syswip Advanced Member level 4 Joined Nov 11, 2009 Messages 119 Helped 12 Reputation 24 Reaction score 4 Trophy points 1,298 Activity points 1,859 STD cell designers can give the better answer. I can only assume that during active low reset design will consume less power. Or in this case it is possible to design flipflop with less transistor. Bests, Tiksan
STD cell designers can give the better answer. I can only assume that during active low reset design will consume less power. Or in this case it is possible to design flipflop with less transistor. Bests, Tiksan
Dec 29, 2009 #4 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,427 Helped 14,752 Reputation 29,786 Reaction score 14,105 Trophy points 1,393 Location Bochum, Germany Activity points 298,127 It's a legacy from TTL and NMOS logic. With CMOS, none of both polarities brings an advantage.
Jan 5, 2010 #5 I iwpia50s Full Member level 4 Joined Oct 31, 2007 Messages 222 Helped 27 Reputation 54 Reaction score 10 Trophy points 1,298 Activity points 2,305 Active low reduces leakage power.