To me this seems like a malformed question.
A FET of any sort has contact resistances in series with
the channel conductance (resistance). Contact resistance
itself ought not respond to gate voltage, it is remote from
the gate and not under its influence. Channel "hookup" to
source, that's another and important deal but is not about
the resistance of a contact feature - has to do with the
engineered spacer and whether it stands off the source
side-diffusion too far, requiring extra channel bias to extend
the channel laterally until it connects to the heavily doped
access region.
This latter, you can see as a Rds(on) at low Vds nonlinearity
as you pass through zero. A well formed MOSFET will look
linear through the origin, a poorly connected one will have
a high Rds(on) below (say) 100mV Vds, which can be
distinguished from the /0 singularity by its breadth-of-region
and curvedness.
It would probablt take specialized structures to separate the
contact, access and channel resistancr contributions - PCM
structures probably have contact and channel, leaving the
access resistance as a de-embed problem?