how are constraints generated in ise
Hi,
the Devices I used is Virtex II xc2v2000 and xc2v3000, and the logic design around 600 K gates. The clock fed in is around 80Mhz and the main system clock inside is 80/3 MHz. the PC I use is 3GHz + 2G memoried.
I ran into quite a lot of trouble to set the detailed constraints,
1.There are clock dividers. It seems that the synplify-pro don't support generated clock, like in DC. The constraints though created for the clock-out from the clock divider, is not applied in the synthesis and will no appeared in the auto-generated NCF files. And as I tried to manually created the same set of constraints in Constraints Editor of ISE, the tool is quite due to unknown errors.
2. some multi-cycle constraints are missing in the auto-generated files, which are proved valid for the SOC design.
3. though the runtimes is 10 times of the run-times of the run with simplest constraints, the results are lowsy.
Finally I decided to use the simple constraints set for pad location, area constraints and the fed in clock frequency(the clock from pad will go through a DCM). the run times is around 15 mins and around half of the results are proved to be successful. This is why I have the above question here.
regards,
Gerade