constraints for Xilinx ISE , useful or not?

[gerade]

xilinx related clock dividers constraint

Hi, all,

in the past months, I have been using Xilinx FPGA to built prototypes. and from my experience with the design flow and observation, I met a "conclusion" that detailed contraints for the synplify-pro && Xilinx iSE flow will help to get a better results. even worse the run time will increase exponentially and aso the memory consumption!!

I assume that I may misunderstand the flow, and there may be something wrong with flow.

can you think of anything that I may make wrong? or is it true that more constraints will really not help much?

thanks and regards,

Gerade

 

[echo47]

generated clock ise constraint

There are hundreds of different constraint types. Which ones are causing you trouble?

The most common constraints are I/O assignments such as LOC and DRIVE. You need them to nail down the I/O characteristics.

If your clock or I/O is pretty fast, then you should use some timing constraints. That improves the chances of getting results that meet your timing goals. For some designs, the only required timing constraint is clock PERIOD.

Constraints usually don't slow down things very much unless your design is inefficient, or you are pushing the chip to its speed limit. Then the constraints will cause the tools to struggle for a long time and possibly fail your timing goals. My approach is to temporarily remove all timing constraints, improve the design until its speed is pretty close to my goals, and then reinsert the constraints.

You need lots of RAM to run ISE. 1GB is a good starting point. 2GB for the big chips.

 

[gerade]

how are constraints generated in ise

Hi,

the Devices I used is Virtex II xc2v2000 and xc2v3000, and the logic design around 600 K gates. The clock fed in is around 80Mhz and the main system clock inside is 80/3 MHz. the PC I use is 3GHz + 2G memoried.

I ran into quite a lot of trouble to set the detailed constraints,
1.There are clock dividers. It seems that the synplify-pro don't support generated clock, like in DC. The constraints though created for the clock-out from the clock divider, is not applied in the synthesis and will no appeared in the auto-generated NCF files. And as I tried to manually created the same set of constraints in Constraints Editor of ISE, the tool is quite due to unknown errors.
2. some multi-cycle constraints are missing in the auto-generated files, which are proved valid for the SOC design.
3. though the runtimes is 10 times of the run-times of the run with simplest constraints, the results are lowsy.

Finally I decided to use the simple constraints set for pad location, area constraints and the fed in clock frequency(the clock from pad will go through a DCM). the run times is around 15 mins and around half of the results are proved to be successful. This is why I have the above question here.

regards,

Gerade

 

[shekar_vlsi]

increase memory xilinx ise 2gb

According to me i think the constraints are related to us because we are the designers and we know how the design should function and so it is our choice to select the constraints for better use