Constraint on Multi-Clock with a same source

[bigdog]

Hello guys,

In my design, we have multiple clocks with different frequency, but the clocks have the same source.
(For example, clock A and clock B both are divided from clock S, and Frequency(A) = n*Frequency(B), n is an integer)
There are some logic between the two clock domains, how can I constraint the logic from clock A to clock B, and the logic from clock B to clock A?

Regards

 

[rsqf]

yep , you could set the generate-clock using the same source clock. Then the STA tools will calculate the setup/hold time in these clock domains.

 

[bigdog]

Yes if I have the whole circuit, the key is that CLKA and CLKB are all input clock, so I can't do that ..

 

[rsqf]

If you can confirm that the clkA and clkB ablosutely come from the same source, and according to the design requirement you do want to check the timing between these domain, you can set these clocks in the same clock group. Then tools will check timing in these domains.

 

[bigdog]

Since the definition of the two clocks are separately, and the frequency are different too, so how to tell DC that the two clocks have a same source?

 

[rsqf]

You could use this command: set_clock_group {}

It defines the group of clock . The detail information you can find in the DC ref doc.