Apply all constraints on the core and synthesize it without IO pads. After synthesis insert IO pads into the netlist using scripts or manually. But if u r inserting PADs into RTL before synthesis, then put a dont touch on all IO pads, and do synthesis.
better to follow bottom-up compile stratagy to acheive better performance. use incremental compile as well.
Apply all constraints on the core and synthesize it without IO pads. After synthesis insert IO pads into the netlist using scripts or manually. But if u r inserting PADs into RTL before synthesis, then put a dont touch on all IO pads, and do synthesis.
You must choose the right IO PAD that has the right/suitable intrinsic timing delay...else you will have to constrain your core design at very high clock frequency to achieve your specification. THough you will be able to achieve your spec, the layout engineer will face difficulties if you have to synthesize your core at 10 times of your spec.