zxvc
Newbie level 5
Hi,
My APR tool is IC Compiler.
I connected all constant nets to tie cells.
After routing, the timing analysis showed there were max_capacitance vioations
at constant nets driven by tie cells and I couldn't fix them.
Could I ignore the constant net DRC violations?
Do these violations make any functional errors?
My APR tool is IC Compiler.
I connected all constant nets to tie cells.
After routing, the timing analysis showed there were max_capacitance vioations
at constant nets driven by tie cells and I couldn't fix them.
Could I ignore the constant net DRC violations?
Do these violations make any functional errors?