Connecting unsigned to std_logic_vector ports

[shaiko]

I'm working on a complicated FPGA project with numerous old blocks that use std_logic_vector type ports (numeric_std library).
The newer blocks that I designed and want to integrate are of type unsigned (std_logic_unsigned).

Can I seemlesly interconnect the 2 types?

 

[TrickyDicky]

please clarify what you mean. The std_logic_vector type is defined in the std_logic_1164 package. Unsigned is defined in the numeric_std package (but annoyingly, it is also defined in the non standard std_logic_arith package). Std_logic_unsigned only contains functions to treat std_logic_vectors as unsigned numbers.

whatever package they are from, std_logic_vector and unsigned are closely related types. They are both arrays of std_logic. Hence you can do a simple type convert between the two:

signal a : std_logic_vector;
signal b : unsigned;

a <= std_logic_vector(b);

or the other way

b <= unsigned(a);

 

[FvM]

It's convenient to use type casts directly in the component instantiation.

 

[shaiko]

is the "std_logic_1164" package a VHDL standart?

 

[TrickyDicky]

yes. It defines the behaviour of std_logic and std_logic_vectors (and std_ulogic and std_ulogic_vector)

 

[shaiko]

If the library that defines std_logic_vectors is a standart library - why isn't the std_logic_vector considered a standart type??

 

[TrickyDicky]

std_logic_vector IS a standard type. But it was not meant to be used as a number - its just a collection of bits.
Because so many people in the late 80s and very early 90s wanted to do arithmatic, synopsys wrote some libraries of its own to do arithmatic with std_logic_vectors - the std_logic_unsigned/signed package. It also (probably later) realised that this went against the idea of strong typing, and so created the std_logic_arith package that defines unsigned and signed types. To make life easy for themselves, but technically break the rules, they compiles the packages into the IEEE library.

the IEEE cottoned on and in 1993 numeric_std became a standard library in VHDL. The problem was that synopsys had distributed their code to vendors (or they had written their own versions of the packages) and engineers had learned to use these non-standard packages (so technically now a defacto standard). The fact that tools didnt support numeric_std for a while didnt help either. Neither did the third fact there were many text books teaching the use of std_logic_unsinged/signed/arith, and this problem still persists OVER 20 YEARS since numeric_std was standardised.

 

[shaiko]

what about math_real?
Do any synthesis tools support it?

 

[TrickyDicky]

math_real is an IEEE standard.
But the real type has no meaning on hardware. It cannot map to individual bits. So the real type (and any packages that provide arithmatic for it - math_real) is not synthesisable (you can use it in testbenches or for settings things up like constants, generates etc)

the VHDL working group kind of addressed this by producing the float_pkg with VHDL 2008. It is fully synthesisable, but of practically no use as I dont know of any tools that will map the functions back to their floating point IP library blocks. Without this ability, the floating point operations complete in a single clock cycle and give you a terrible FMax. Someone must have asked for it - maybe it has some use in ASICs?

 

[K-J]

what about math_real?
Do any synthesis tools support it?

For the purposes of calculating constants, math_real is typically supported. The same can be said for type 'time'.

Kevin Jennings