Connecting tri-state buffers

[shaiko]

Most modern FPGAs don't have internal tri-state buffers.
However, what if I want to connect an INOUT port of a VHDL component with an INOUT port of the top entity (a simple wire) ?
Will all synthesis tools peacefully obey ?

 

[TrickyDicky]

internally connected tristates are generated via muxes instead, so inouts should work properly.

 

[shaiko]

Do you mean they're simply wired to a tristate buffer at the FPGA pin ?

 

[TrickyDicky]

no, if you try and wire together a tri state buffer on internal logic, the synthesisor will convert them to muxes.
As for internal inouts, I wouldnt recommend it - but it should just create muxes for you.

 

[shaiko]

Why? these "internal" INOUTs aren't really internal...
They're wired directly to the top entity. Please see the attached picture at the first post.

 

[TrickyDicky]

Sorry - wasnt paying attention.
Basically, the VHDL heirarchy is just an abstration. The buried entity is just wired to the IO pin on the device. So it will work properly.

 

[shaiko]

Basically, the VHDL heirarchy is just an abstration

That's what I thought...however Xilinx ISE 13.2 thinks otherwise.
It degenerates the ports (together with the logic behind them) connecting the pins to a pull-up.

I was really baffled by it, so I compiled the same code with Quartus and it synthesized flawlessly.
Any ideas ?

 

[TrickyDicky]

I dont have much experience with Xilinx tools. But I do know it's pretty shitty at doing anything with VHDL.

 

[std_match]

The VHDL language itself has no problem with this, but some synthesis tools can't handle it. In general, it doesn't work for ASIC synthesis. FPGA tools should be able to handle it, but I have not tried it much. I normally use separate in, out and direction signals all the way to the top entity. With this method, sub-blocks can be used both in FPGA's and ASIC's.

 

[shaiko]

In general, it doesn't work for ASIC synthesis.

Why not?
As TrickyDicky said, it's just an abstraction...no real logic is described.

 

[std_match]

Why not?
As TrickyDicky said, it's just an abstraction...no real logic is described.

You must explicitly connect to the I/O buffers, and they don't have tristate signals on the "inside".
The "core" logic is separated from the "I/O ring", and the signals between them must be "in" and "out" only.
Remember that it is common to have different supply voltages for the "core" and the "I/O ring".
The "core" is synthesized separately, so it is impossible to use "inout" signals.
Tristate signals on pins must in the "core" be described as "data in", "data out" and "direction".

To use "inout", the synthesis tool must automatically decide where the separation between "core" and "I/O ring" should be.
That is not very difficult for an FPGA, but such a tool would only create problems for ASIC design.